1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device having a PNPN type memory cell.
2. Description of the Prior Art
Many bipolar semiconductor memory devices used in recent years employ memory cells with diode loads or Schottky barrier diode (SBD) loads. It is well known, however, that memory cells of this type are not suitable for large capacity high integration density memory devices in which the hold current must be made small. In such memory devices, the resistance values of the memory cells must be made large to make the hold current small. Accordingly, it is difficult to make the cell area small.
Recently, PNPN type memory cells with PNP load transistors or NPN load transistors and I.sup.2 L type memory cells have come under scrutiny. Of these two types of memory, it is known that the I.sup.2 L type is generally not able to achieve as high a speed of operation as the PNPN type memory cell.
Conventional semiconductor memory devices having PNPN type memory cells, however, suffer from several drawbacks.
For example, since a buried layer cannot be used as a wiring layer, as in an I.sup.2 L type memory cell, it is necessary to connect the word lines and the bit lines through contact windows. This results in an increased memory cell area. Also, since the load transistor is formed laterally, the characteristic values of the memory cell vary randomly, which slows the switching speed.